
88
8018P–AVR–08/10
ATmega169P
13.4
Register Description for I/O-Ports
13.4.1
MCUCR – MCU Control Register
Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See
”Con-13.4.2
PORTA – Port A Data Register
13.4.3
DDRA – Port A Data Direction Register
13.4.4
PINA – Port A Input Pins Address
13.4.5
PORTB – Port B Data Register
13.4.6
DDRB – Port B Data Direction Register
13.4.7
PINB – Port B Input Pins Address
Bit
7
6
5
4
3
2
1
0
0x35 (0x55)
JTD
-
-PUD
–
IVSEL
IVCE
MCUCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
Bit
765
43
210
0x02 (0x22)
PORTA7
PORTA6
PORTA5
PORTA4
PORTA3
PORTA2
PORTA1
PORTA0
PORTA
Read/Write
R/W
Initial Value
0
Bit
765
43
210
0x01 (0x21)
DDA7
DDA6
DDA5
DDA4
DDA3
DDA2
DDA1
DDA0
DDRA
Read/Write
R/W
Initial Value
0
Bit
765
43
210
0x00 (0x20)
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
PINA
Read/Write
R/W
Initial Value
N/A
Bit
765
43
210
0x05 (0x25)
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
PORTB
Read/Write
R/W
Initial Value
0
Bit
765
43
210
0x04 (0x24)
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
DDRB
Read/Write
R/W
Initial Value
0
Bit
765
43
210
0x03 (0x23)
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
PINB
Read/Write
R/W
Initial Value
N/A